Design of Directed Exponential-step LoopTopologies for HPC Interconnects

The increase of the scale of high performance computing (HPC) system leads to communication delay and physical cable length increase. Thus, we proposed a novel directed exponential-step loop topology for HPC interconnections. Simulation results show that:compared to the random-step counterpart, it can further reduce the communication latency by up to 30 percent, and meanwhile, reduce packaging complexity and physical cable length; Contrary to fixed-step and random-step topologies that calculate communication latencies after generating the topologies, the proposed scheme is able to estimate the latencies before generating the topologies.Besides, this paper extensively compares the proposed exponential-step with the fixed-step and random-step topologies in terms of delay, packaging complexity and physical cable length, scalability.